1. Field of the Invention
The present invention relates to a method, apparatus and program for designing circuits.
2. Related Art
Designing semiconductor integrated circuits includes a plurality of steps, such as designing IP (intellectual property) blocks, assembling the blocks, inserting a test circuit, producing a netlist (logic cell connecting information), and creating a layout. At the step of creating a layout, information (such as on asynchronous relationship for dividing a clock tree so that no portions would be duplicated, and on leaves other than flip flops) required for CTS (clock tree synthesis) is extracted, for example, based on clock information. (See, for example, Japanese Patent Laid-Open No. 2006-85595).
Recently, system LSIs (large scale integrated circuits) tend to have a complicated clock control circuit (circuit covering from a point where clocks are produced, up to leaves, such as flip flops and memories, where the clocks are supplied) because of the increase in the number of clock systems accompanying the scaling up of the LSIs and addition of multiple functions to the LSIs, and also because of the division of design labor between blocks and operational modes.
For this reason, it takes considerable time to analyze the circuit structure of such a clock control circuit and prepare its clock system diagram, and then to carry out logic extraction of the clock control circuit, which has led to prolonging the period required for circuit designing.
In addition, a difficulty has arisen in grasping the functions of an entire clock control circuit, including clocks that propagate in respective operational modes. This has caused another difficulty in the optimization of a clock control circuit carried out prior to the step of creating a layout, the optimization including reduction of a chip area or reduction of the clock latency by the reduction of redundant circuits.